In a world of ever-increasing Internet traffic and exploding mobile usage, the demands on telecom infrastructures to handle the rapidly growing data and video traffic become increasingly challenging. According to Cisco’s Visual Networking Index Global IP Traffic Forecast, 2014-2019, there will be 4 billion global Internet users (more than 51% of the world’s population) and 21 billion networked devices and connections by 2018.
25 Gigabit Ethernet (25GbE) is taking off fast, and many analysts expect it to grow exponentially over the next four years. Imagine the complexity of designing wired network equipment to support a plethora of standards and imploding data rates with minimal packet loss and latency!
With increasing data rates, the link jitter budget gets tighter and tighter. Hardware engineers focused on getting their entire line card designed to support the maximum throughput allocate the minimal possible budget for the random jitter contribution of the reference clock. The maximum possible root mean square (RMS) jitter allowable for the reference clock could range anywhere from 100fs to 300fs for a 25GbE link (integration range from 12 kHz-20 MHz). This standard phase-noise integration range of 12 kHz-20 MHz includes contributions from phase-locked loop (PLL) in-band and out-of-band (VCO) noise. The phase-noise performance of the reference clock generator needs to be excellent both within and outside the PLL loop bandwidth to meet tighter jitter specification requirements.
For example, the LMK03328 offers the industry’s lowest phase-noise floor and consistent RMS jitter in multiple integration bandwidths. The ultra-low phase noise and jitter translates to improved bit error rates (BERs) of the serial link. Consider the improvement over a conventional high-end surface acoustic wave (SAW)-based oscillator. Figure 1 demonstrates a 3x improvement in BER using the LMK03328 compared to a SAW oscillator on a 10G link with a 156.25MHz reference clock. With further optimization, you can achieve even higher performance – as much as a 9x improvement over conventional SAW oscillators.
Figure 1: 10G link performance of SAW oscillator and TI’s LMK03328
A low-phase-noise reference clock translates to a higher jitter-budget allocation for other critical blocks in the serial link. With data rates quickly creeping upwards of 25GbE and permissible BER becoming standard at 1e-18, the importance of a high-quality, low-jitter reference clock to preserve signal integrity becomes paramount.
Having tackled the problem of getting the link to be operational with an open eye, you now need to make sure that your design is robust and operational under stress. The common culprit that deteriorates link signal integrity is power-supply variation. Having integrated low-dropout regulator (LDO) can greatly help overcome susceptibility to supply noise. A clock generator with built-in LDOs greatly helps improve error-free data transmission by providing robust supply noise immunity and excellent power supply rejection ratio (PSRR). Figure 2 shows the improved PSRR and TX eye performance using the LMK03328 since it has integrated LDOs.
Figure 2: PSRR of a SAW oscillator and TI’s LMK03328 clock generator
Leave us a note below in the comments section and let us know what application you're working on that could most benefit from ultra-low jitter.
Additional resources
- Read the LMK03328 datasheet.
- View an LMK033x8 demonstration video.
- Learn more about TI’s clock-generator portfolio.
- Read TI’s application note, “Clocking high-speed serial links using LMK03328.”
- Read TI’s application note, “Frequency margining using TI’s high-performance clock generators.”