Generating bias current networks with arbitrary magnitudes - Part one

As discussed in the previous post in this series, generating DC currents of arbitrary magnitude is a simple and straightforward process using opamp feedback and a voltage reference. However, suppose it was necessary to generate some arbitrary number (N, for example) of current sinks (or sources) each with its own arbitrary magnitude; perhaps to bias the various stages of some complex analog circuitry. While the reference voltage generation only requires a single implementation, repetition of the entire feedback portion of the sink could become cost- and design area-intensive. So a question emerges: Is it possible to implement such a bias network using a single feedback source? The answer is yes—though it gets somewhat complicated and certain conditions must be met—and this network (sink only for this analysis) is shown in Figure 1 below. 

Figure 1: Current Sink Network 

Ultimately the source voltage of the MOSFET, V_S, and the R_SET resistor determine the sink current in each leg; by removing the feedback from the outer sink legs (that is, for all N > 1), direct control of V_SN has been lost. Thus, R_SETN must be carefully selected to generate the desired, arbitrary Nth leg sink current, I_SINKN. Examining Figure 1 above, an equation can be readily derived which defines the ratio of the current in the Nth leg of the bias network to that of the first: 

Rearranging Equation 1 in to solve for the R₁ to R_N resistor ratio, M_RN, yields:

So what is the MOSFET source voltage in the Nth leg of the bias network, V_SN? Consider the drain current equation for an NMOS operating in the saturation region: 

It is important to note that the effects of channel width modulation can be largely ignored here. This is because any increase in drain current from an increasing drain voltage would drop across the R_SET resistor and result in an increased source voltage. In order for the MOSFET to maintain any current whatsoever, the gate voltage must be larger than the source and threshold voltages combined. That is, for a fixed gate voltage, the source voltage is ultimately clamped to at least a threshold voltage drop below it, and no amount of drain voltage increase will increase drain current. Therefore, establishing the operating condition that R_SET must be sufficiently large to ensure this clamping allows the following assumption to be made:

 The ratio expressed in Equation 1 can now be rewritten based on Equations 3 and 4:

In order to simplify Equation 5, the following term can be defined:

After making this substitution and rearranging terms in Equation 5, an equation for V_SN can be derived: 

Substituting Equation 8 into Equation 2 yields:

So what is the gate drive to threshold voltage difference, V_GT? This is ultimately determined by the feedback in the first leg of the bias network; it is essentially the voltage required to maintain the desired I_SINK1 current:

After rearranging terms in Equation 11, an equation for V_GT can be determined: 

Substituting Equation 13 into Equation 10 yields:

Finally, the resistor ratio M_RN can be written as a solely a function of M_IN (along with some physical constants of the bias network devices) as follows: 

Now that an equation modeling the R_SET resistor ratio has been derived; it’s implications on producing a bias current network with arbitrary magnitudes can be explored—the topic of the next blog in this series.