Pass your power bank EMI test

A key design challenge for designing a power bank is passing the EMI test.  Electronics engineers often fear about the EMI test failure. And it would be a nightmare if the circuit failed the EMI again and again. You would have to work day and night in the EMI lab to fix the problem to avoid product launch delays. For the consumer products like power banks, the design period is short, while the EMI certification limit is strict, so you would like to add enough EMI filters to pass the EMI test smoothly, but you also don’t want to increase the space and add much cost to the circuit. It seems hard to achieve both. 

The TI design Low Radiated EMI Boost Converter Reference Design (PMP9778) provides such a solution. It can support 2.7 - 4.4V input voltage, 5V/3A, 9V/2A and 12V/1.5A output power and just fit for the power bank application. By optimization of the placement and layout, this TI design can get higher than 6dB margin in the EN55022 and CISPR22 class B radiation test. Let’s take a look at the design process.

Identify Critical Current Path

EMI starts off from the high instantaneous rate of current change (di/dt) loops. So we should differentiate the high di/dt critical path at the beginning of the design. To achieve these, it is important for us to understand the current conduction paths and signal flows in the switching power supply.

Figure 1 shows the topology and critical current path of the boost converter. When S2 closed and S1 opens, the AC current flows through the blue loop. When S1 closed and S2 opens, the AC current flows through the green loop. So the current flows through input capacitor Cin and inductor L is a continuous current, while the current flows through the S2, S1 and the output capacitor Cout is a pulsating current (red loop). So we define the red loop as the critical current path. This path has the highest EMI energy. We should minimize the area enclosed by it during the layout.

Figure 1. Critical Current Path of Boost Converter

Minimize High di/dt Path Loop Area

Figure 2 shows the pin configuration of the TPS61088. Figure 3 shows the TPS61088 critical current path layout example. The NC pin means no connection inside the device. So they can be connected to PGND.  From electrical point of view, connecting the two NC pins to the PGND ground plane is good for thermal dissipation and can reduce the impedance of the return path. From EMI point of view, connecting the two NC pins to the PGND ground plane makes the VOUT and PGND plane of the TPS61088 much closer to each other. And this makes the placement of the output capacitors much easier. From figure 3, we can see that placing one 0603 1-uF (or 0402 1-uF) high frequency ceramic capacitor C_{OUT_HF} as close to the VOUT pin as possible results in minimum area of the high di/dt loop.

Figure 2. TPS61088 Pin Configuration

Figure 3.  TPS61088 Critical Path Layout Example

The maximum electric field strength from such a high di/di loop over a ground plane at a 10 meter distance can be calculated by the following equation:

Where A is the loop area,  is the current flowing in the loop,   is the interested frequency of . So smaller critical path area means smaller radiation energy.

Figure 4 shows the radiated EMI result with and without C_{OUT_HF}. Under the same test condition, the radiated EMI is improved by 4dBuV/m with C_{OUT_HF}.

Figure 4. Radiated EMI Result With and Without C_{OUT_HF}

Putting a Ground Plane under the Critical Path

High trace inductance leads to poor radiation EMI. Because the magnetic field strength is in direct proportion to the inductance. Placing a solid ground plane on the next layer of the critical trace can solve this problem.         

Table 1 gives out the inductance of a given trace on different PCB boards. We can see that for a 4-layer PCB with 0.4 mm insulation thickness between the signal layer and the ground plane, the trace inductance is much smaller than that of a 1.2 mm thickness 2-layer PCB. So putting a solid ground plane with minimum distance to the critical path is one of the most effective ways to reduce the EMI.

Table 1. Trace Inductance (Trace Length = 5cm)

Figure 5 shows the radiated EMI result of a 2-layer PCB and a 4-layer PCB. Under the same layout and same test condition, the radiated EMI is improved by more than 10dBuV/m with a 4-layer PCB.

    Figure 5. Radiated EMI Result of a 2-Layer PCB and a 4-Layer PCB

Adding RC Snubber

If the radiation level still exceed the requirement level and the layout cannot be improved anymore, then adding a RC snubber across the TPS61088’s SW pin and the power ground can help in reducing the radiation EMI levels. The RC snubber should be placed as close as possible to the switching node and the power ground (Figure 6). It can effectively damp out SW voltage ring, which means the radiated EMI at the ringing frequency can be improved.

Figure 6. Placement of RC Snubber

With the above simple yet effective optimizations, good EMI performance is possible in power bank designs. Besides power bank applications, this TI design also fit for blue-tooth speaker, portable POS terminals and E-cigarette applications and more. Start your design process now by downloading the Low Radiated EMI Boost Converter Reference Design. Additional resources:

• Read more power banks blogs.